1. Field of the Invention
The present invention relates to a method of manufacturing an MOS semiconductor device having a parallel plate capacitor. More particularly, the present invention relates to a simultaneous formation of a parallel plate capacitor and an MOS transistor.
2. Description of the Related Art
Heretofore, in a method of manufacturing an MOS semiconductor device having a polysilicon-insulator-polysilicon polisilicon (PIP) parallel plate capacitor, an upper electrode and a lower electrode of a capacitor made of polycrystalline silicon are typically formed after forming a gate electrode of an MOS transistor in a process separate from the gate electrode forming process.
The forming method according to the prior art will be described with reference to FIG. 1. As shown in FIG. 1A, a field oxide film 102 is formed on a silicon substrate 101 by the LOCOS (Local Oxidation of Silicon) method, thereby performing the device isolation. Subsequently, after controlling the threshold values of the well forming region and the MOS transistor forming region by means of the ion implantation method and the ion diffusion method, a gate insulating film and a gate electrode film are formed. Thereafter, a gate electrode 103 is formed by the photolithography etching technique.
Then, after forming an MOS transistor by the ion implantation method and the ion diffusion method, an intermediate insulating film 104 made of a silicon oxide film is deposited on the gate electrode, and the surface thereof is planarized by the CMP (Chemical Mechanical Polishing) method. Then, a polycrystalline silicon film to be a lower electrode of a capacitor is deposited, and a lower electrode of a capacitor 105 is formed by the photolithography etching method. Subsequently, after forming a capacitor insulating film 106, a polycrystalline silicon film to be an upper electrode of a capacitor is deposited, and an upper electrode of a capacitor 107 is formed by the photolithography etching method. (FIG. 1B).
Then, after an interlayer insulating film 108 made of, for example, a silicon oxide film is deposited and planarized by the CMP method, a contact hole 109 on an active region, a contact hole 110 on the gate electrode, a contact hole 111 on the lower electrode of a capacitor, and a contact hole 112 on the upper electrode of a capacitor are formed by the photolithography etching method (FIG. 1C). Finally, after the contact holes 109, 110, 111, and 112 are buried with a buried metal 113 such as tungsten, a wiring layer 114 is formed (FIG. 1D).
In the prior art, however, since three processes for forming a gate electrode, forming a lower electrode of a capacitor, and forming an upper electrode of a capacitor are necessary, the entire process becomes complicated, and resulting in the increase of the manufacturing cost. Also, since the lower electrode of a capacitor and the upper electrode of a capacitor are formed after forming an MOS transistor, the impurity profile of the MOS transistor is influenced by the thermal treatment performed when forming the capacitor, which makes it difficult to achieve more downsizing of the MOS transistor.
For the solution of the problems described above, the present invention provides a method in which a buried electrode of a buried MOS transistor formed in a trench which is formed in an active region and a lower electrode of a capacitor formed on a device isolation are simultaneously formed by means of the etching of a polycrystalline silicon. The method makes it possible to easily manufacture an MOS semiconductor device having a fine MOS transistor and a PIP flat plate capacitor in a simple process.